The present invention relates to a timing adjustment circuit for producing an internal clock signal which has a predetermined phase relation with respect to an inputted external clock signal and to a semiconductor device including the timing adjustment circuit.
In semiconductor devices such as a synchronous memory which operates in synchronization with an external clock signal (clock synchronous type semiconductor memories such as SDRAM) and a controller (a system LSI or microprocessor), with speeding-up of the operation, a propagation delay of a clock signal in an apparatus has raised a problem. To solve the problem, in the conventional semiconductor device, a timing adjustment circuit is disposed in an interface (or an input/output device) to receive an external clock signal and to produce an internal clock which has the same phase as that of the external clock signal, or a predetermined phase difference.
Additionally, the semiconductor device has further been speeded up in recent years (frequency of the external clock has been increased). Accordingly, there has been a problem that a phase difference between the external clock signal and the internal clock signal deviates from a predetermined value (timing deviation). Specifically, with enhancement of an operation rate of the semiconductor device, an allowable range is narrowed with respect to the timing deviation, and a manufacturing fluctuation which is a cause for the timing deviation has raised a problem.
To solve such a problem, it has been proposed to compare the phase of the external clock signal with that of a data signal outputted from an output circuit in synchronization with the internal clock signal and to adjust a delay time of a replica circuit (or a dummy load) included in the timing adjustment circuit based on the comparison result (e.g., see Japanese Unexamined Patent Publication No. 2000-163999, pages 4–5, FIGS. 2, 5 and 7).
Referring to FIG. 1, description will be made of such a timing adjustment circuit. A timing adjustment circuit 50 includes: a clock input circuit 52 for receiving an external clock signal CLK supplied to an external clock input terminal 51 to output an input clock signal; a phase/delay adjustment circuit 53 including a delay locked loop (DLL) or a phase locked loop (PLL) for delaying the input clock signal from the clock input circuit 52; a clock driver 54 for receiving a delay input clock signal from the phase/delay adjustment circuit 53 to output the internal clock signal; a replica circuit 57 for generating a delay in accordance with a data output circuit 55 (or a data strobe output circuit 56) driven by the clock driver 54; and a phase comparison circuit 58 for comparing the phase of the output signal (feedback signal) of the replica circuit 57 with that of the external clock signal to output a comparison result to the phase/delay adjustment circuit 53. It is to be noted that the replica circuit 57 is constituted to be capable of adjusting the delay.
The timing adjustment circuit 50 produces the internal clock signal for defining a timing at which data is outputted from the data output circuit 55, and feedback-controls the delay of the phase/delay adjustment circuit 53 so that the phase of the feedback signal from the replica circuit 57 agrees with that of the external clock signal. At this time, when the phase of an output signal Dout of the data output circuit 55 agrees with that of the feedback signal, the phase/delay adjustment circuit 53 is feedback-controlled, and accordingly the phase of the output signal of the data output circuit 55 agrees with that of the external clock signal.
Additionally, when timing deviation exists in the timing adjustment circuit 50 by manufacturing fluctuation, and even when the phase/delay adjustment circuit 53 is feedback-controlled as described above, the phase of the output signal of the data output circuit 55 does not agree with that of the external clock signal CLK. In this case, the timing deviation by the manufacturing fluctuation is removed as follows.
First, “0” and “1” are alternately repeatedly outputted from the data output circuit 55 in synchronization with the internal clock signal. When the data strobe output circuit 56 is used, a data strobe signal is used as such.
Subsequently, a test apparatus (not shown) is used to detect the phase (rising edge) of the external clock signal CLK supplied to the external clock input terminal 51, and the phase (change point) of the output signal of the data output circuit 55 (or the data strobe output circuit 56) outputted to a data output terminal 59. Moreover, these phases are compared with each other, and the delay of the replica circuit 57 is adjusted based on a phase difference.
Then, the test apparatus is used again to compare the phases of the signals with each other so as to check whether the phase of the output signal of the data output circuit 55 agrees with that of the external clock signal.
Thereafter, the above-described operation is repeated until the phase of the output signal of the data output circuit 55 agrees with that of the external clock signal CLK.
Here, the replica circuit 57 will be explained. For example, the replica circuit 57 is constituted to be capable of changing the delay in accordance with a value stored in a register, or to be capable of changing the delay by disconnecting a fuse (one or a plurality of fuses in a fuse group). The replica circuit 57 further includes a switch for selecting one of the register and fuse (group). When the phases of two signals are compared with each other as described above while adjusting the delay of the replica circuit 57, the register is selected, and the value stored in the register is changed to adjust the delay. Further, when the phase of the output signal of the data output circuit 55 agrees with that of the external clock signal, the fuse is disconnected so as to realize the delay. Moreover, the switch is changed over to a fuse side from a register side to fix the delay of the replica circuit 57.
As described above, in the timing adjustment circuit 50 illustrated in FIG. 1, the problem of the timing deviation by the manufacturing fluctuation can be solved.
The above-described timing adjustment circuit 50 adjusts the output timing of the delay from the data output circuit 55, but a timing adjustment circuit for adjusting an input timing of a data input circuit is also disposed. One example of this timing adjustment circuit is shown in FIG. 2.
A timing adjustment circuit 60 illustrated in FIG. 2 includes: a clock input circuit 62 for receiving the external clock signal CLK supplied to an external clock input terminal 61 to output an input clock signal; a delay adjustment circuit 63 for delaying the input clock signal; and a clock driver 64 for receiving the delayed input clock signal to output the internal clock signal.
This timing adjustment circuit 60 produces the internal clock signal for defining the operation timing of a data input circuit 66 which latches the input data supplied to a delay input terminal 65. The phase of the data signal outputted from the data input circuit 66 may have a predetermined relation with that of the external clock signal CLK, and the phases do not have to necessarily agree with each other. Therefore, in the timing adjustment circuit 60, the feedback control is not performed as in the timing adjustment circuit 50 of FIG. 1.
In this timing adjustment circuit 60, the delay of the delay adjustment circuit 63 can be adjusted to remove the timing deviation. Specifically, the phase of the data signal outputted from the delay input circuit 61 is compared with that of the external clock signal CLK, the delay of the delay adjustment circuit 63 is adjusted so that the phase difference indicates a predetermined value, and thereby, the timing deviation is removed. For example, the delay adjustment circuit 63 is structured by a register, fuse, and switch in the same manner as in the replica circuit 57 of FIG. 1.
In the conventional timing adjustment circuit, in order to remove the timing deviation by the manufacturing fluctuation, two signals including the external clock signal and the output signal of the data output circuit or the data input circuit are detected, and the phases have to be compared with each other. In other words, a test apparatus including two pins (input terminals) is required for detecting two signals.
However, in a low-precision test apparatus for use in wafer tests, a skew between the pins is 1 ns or more, and is larger than the timing deviation (about 500 ps) allowed in a device, for example, which operates with an external clock of 500 MHz. Therefore, the conventional timing adjustment circuit cannot detect or remove the timing deviation using the low-precision test apparatus. That is, the conventional timing adjustment circuit has a problem that the circuit is limited by the skew between the pins in the test apparatus for use, when removing the timing deviation.